Those of us familiar with solid state electronic devices and elements such as the CMOS and BJT are aware of equivalent shunt capacitance elements which appear scattered across almost every circuit but are effective only at fairly high frequencies or switching transitions. Textbooks tell us that these elements are parasitic. The word is slightly unnerving, as it suggests that these elements are unwanted and undesirable. While some of their outcomes might be undesirable to zeroth order circuit designers, it is important to note that these elements appear not because of non-idealities but rather because of the model itself. To qualify this statement, that these capacitive elements exist is completely consistent with the quantum transport in these devices at high frequencies or switching currents. Theory predicts that these elements should exist.
Now, consider a scenario involving a dynamic CMOS logic circuit where all the CMOS transistors have zero shunt capacitance (and hence infinite impedance paths at suitable junctions to ground). There is no location to store the charge in the alleged precharge interval and therefore also no source for the pull down transistor network to sink the charge from a storage device in the evaluation interval. With no capacitances in this network, how would a dynamic CMOS logic circuit work? While this is a fairly simple example of the absence of parasitic capacitance leading to what the idealists might regard as a paradox, there are several other examples in electromagnetic theory where capacitances and even inductances are unavoidable and in fact predicted by theory, e.g. in transmission lines, interconnects, ground bounces, etc. The moral is not to treat the word 'parasitic' in parasitic elements too literally, and reconcile with their existence by appealing to complete or at least refined device physics models.
Now, consider a scenario involving a dynamic CMOS logic circuit where all the CMOS transistors have zero shunt capacitance (and hence infinite impedance paths at suitable junctions to ground). There is no location to store the charge in the alleged precharge interval and therefore also no source for the pull down transistor network to sink the charge from a storage device in the evaluation interval. With no capacitances in this network, how would a dynamic CMOS logic circuit work? While this is a fairly simple example of the absence of parasitic capacitance leading to what the idealists might regard as a paradox, there are several other examples in electromagnetic theory where capacitances and even inductances are unavoidable and in fact predicted by theory, e.g. in transmission lines, interconnects, ground bounces, etc. The moral is not to treat the word 'parasitic' in parasitic elements too literally, and reconcile with their existence by appealing to complete or at least refined device physics models.
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